Network computer systems generally include a plurality of geographically separated or distributed computer nodes that are configured to communicate with each other via, and are interconnected by, one or more network communications media. One conventional type of network computer system includes a network storage subsystem that is configured to provide a centralized location in the network at which to store, and from which to retrieve data. Advantageously, by using such a storage subsystem in the network, many of the network's data storage management and control functions may be centralized at the subsystem, instead of being distributed among the network nodes.
One type of conventional network storage subsystem, manufactured and sold by the Assignee of the subject application (hereinafter “Assignee”) under the trade name Symmetrix™ (hereinafter referred to as the “Assignee's conventional storage system”), includes a plurality of disk mass storage devices configured as one or more redundant arrays of independent (or inexpensive) disks (RAID). The disk devices are controlled by disk controllers (commonly referred to as “back-end” I/O controllers/directors) that may store user data in, and retrieve user data from a shared cache memory resource in the subsystem. A plurality of host controllers (commonly referred to as “front-end” I/O controllers/directors) also may store user data in and retrieve user data from the shared cache memory resource. The disk controllers are coupled to respective disk adapters that, among other things, interface the disk controllers to the disk devices. Similarly, the host controllers are coupled to respective host channel adapters that, among other things, interface the host controllers via channel input/output (I/O) ports to the network communications channels (e.g., SCSI, Enterprise Systems Connection (ESCON), and/or Fibre Channel (FC) based communications channels) that couple the storage subsystem to computer nodes in the computer network external to the subsystem (commonly termed “host” computer nodes or “hosts”).
In the Assignee's conventional storage system, the shared cache memory resource may comprise a plurality of memory circuit boards that may be coupled to an electrical backplane in the storage system. The cache memory resource is a semiconductor memory, as distinguished from the disk storage devices also comprised in the Assignee's conventional storage system, and each of the memory boards comprising the cache memory resource may be populated with, among other things, relatively high-speed synchronous dynamic random access memory (SDRAM) integrated circuit (IC) devices for storing the user data. The shared cache memory resource may be segmented into a multiplicity of cache memory regions. Each of the regions may, in turn, be segmented into a plurality of memory segments. In each of the memory boards, the majority of the internal circuitry is configured to process parallel control and data words.
It has been proposed to configure the shared cache memory resource to use serial bit stream transmission to exchange user data and related control information (e.g., comprising address and memory command information, etc.) with the host controllers and disk controllers. In order to be able to implement this, it would be necessary to provide in each memory board respective circuitry to convert into corresponding parallel words the serial bit stream transmissions received by the memory board from host and disk controllers. For this purpose, it has been proposed to use, in each respective cache memory board conventional “off-the-shelf” discrete integrated circuit (IC) chips comprising serial-to-parallel converter circuitry that may be configured to convert into corresponding parallel words the serial bit stream transmissions received by the respective memory board. The internal control circuitry in the respective memory board may be configured to examine these parallel words, determine therefrom the respective portions of user data and related control information embedded therein, forward the respective parallel words of user data to a first-in-first-out (FIFO) memory for later processing, decode the related control information, and cause the parallel words of user data to be processed by the respective memory board in accordance with the related control information.
In a respective memory board, the rate at which a respective serial bit stream may be received and processed by the respective serial-to-parallel converter circuitry, and the rate at which the parallel words of user data may be stored in the FIFO memory, may be governed by a first clock signal generated in the host or disk controller and used to generate the bit stream, but the rate at which the respective memory board's internal control circuitry may seek to retrieve the parallel words of user data from the FIFO may be governed by a second clock signal generated inside the respective memory board. Thus, the respective rates at which the FIFO may be filled with, and emptied of, user data may be different.
In order to try to prevent the FIFO memory from filling too quickly (and thereby possibly overwriting valid user data that has yet to be retrieved from the FIFO by the memory board's control circuitry), or emptying too quickly (and thereby possibly causing the same user data to be retrieved twice by the control circuitry), a relatively complex, “elastic” FIFO buffer memory may be employed as the FIFO memory in the serial-to-parallel converter circuitry. This elastic FIFO buffer memory may be configured to receive and store, at a rate governed by the first clock signal, the parallel words of user data generated by the converter circuitry. The elastic FIFO memory may also be configured to permit the parallel words of user data stored therein to be retrieved therefrom by the memory board's internal control circuitry at a rate governed by the second clock signal.
The elastic FIFO/buffer memories used in such conventional serial-to-parallel converter circuitry typically comprise relatively complex circuitry, may require undesirably large amounts of processing overhead to carry out their respective operations, and may introduce sources of potential unreliable processing behaviors into the cache memory resource. Also, the presence in a respective memory board of the discrete IC chips that comprise such conventional serial-to-parallel converter circuitry introduces into the respective memory board another stage, or hop, that the user data and related control information must propagate through when the data and related control information move from the host/disk controllers to the respective memory board's internal circuitry; this may increase latency in moving data and related control information from the host/disk controllers to the respective memory board's internal control circuitry, and reduce the efficiency of transfers of user data and related control information from the host/disk controllers to the respective memory board's internal control circuitry.
Accordingly, it would be desirable to eliminate the need to use, in the respective memory boards of the shared cache memory resource, the aforesaid type of discrete IC chips that comprise such conventional serial-to-parallel converter circuitry (and in particular, the elastic FIFO memories comprised in such conventional serial-to-parallel converter circuitry) while still permitting the host/disk controllers to transmit user data and related control information to such memory boards using serial bit streams.